Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a buried gate, a storage node and a bit line, and a method for manufacturing the same.
A Dynamic Random Access Memory (DRAM) includes a plurality of unit cells, each of which includes a capacitor and a transistor. The capacitor is used to temporarily store data therein. The transistor is used to transmit data between a bit line and the capacitor in correspondence with a control signal (i.e., a word line) using the electric conductivity of a semiconductor material, which changes depending on environment. The transistor has three regions including a gate, a source and a drain, and charges between the source and the drain move in response to the control signal input to the gate. The charges between the source and the drain move through a channel region in accordance with the properties and operation of the semiconductor device.
When a general transistor is formed in a semiconductor substrate, the gate is formed in the semiconductor substrate, and impurities are doped at both sides of the gate to form the source and the drain. In this case, a region between the source and the drain under the gate becomes the channel region of the transistor. A transistor that has a horizontal channel region occupies a predetermined area of the semiconductor substrate. Reducing the overall area of a complicated semiconductor memory apparatus is difficult due to the plurality of transistors contained in the semiconductor device.
If the overall area of the semiconductor memory apparatus is reduced, the number of unit cells per wafer is increased, resulting in increased productivity. A variety of methods have been proposed to reduce the overall area of the semiconductor memory device. A representative method uses a recess gate wherein a recess is formed in a substrate and a gate is formed in the recess such that the channel region is formed along a curved surface of the recess, instead of using a conventional planar gate having a horizontal channel region. With the progress of the above recess gate, another method for burying the entirety of the gate in the recess to form a buried gate has also been proposed.
In the buried gate structure, an isolation gate in a line type is used to define a bit line contact and a storage node contact. However, the isolation gate structure increases a leakage current in a cell area more than a trench-type device isolation film.
When patterning a bit line contact in the buried gate structure employing a trench-type device isolation film, the contact hole must be patterned as a hole type and a dry etch process must be used for such patterning. If the pattern size implemented in a given process condition is reduced, a contact hole pattern may not be defined on a mask. In addition, when etching a contact hole in an active region in a subsequent etch process, the active region may not be opened. If the contact hole size is increased to prevent the above-mentioned problems, short-circuiting may occur between the contact hole and the storage node.
The storage node contact must be formed by a Self Aligned Contact (SAC) process after bit-line formation, and contact resistance unavoidably increases as a contact area between the active region and the contact is reduced.